This invention relates to pulse width modulation and more particularly to a logic design which significantly reduces the number of required logic blocks and the size of the chip containing the pulse width modulation logic.
Typically, for pulse width modulation using digit delay, a logic design with numerous logic blocks such as D flip flops are needed. Referring to FIG. 1, there is shown a prior art logic diagram which utilizes four positive edge triggered D flip flops to delay a signal for 4 mclock cycles. Referring to FIG. 2, there are shown signals of a clock C, an input signal D, and output signals D.sub.1, D.sub.2, D.sub.3, and D.sub.4. Referring to both FIGS. 1 and 2, the input signal D is applied to DF.sub.1 which will be held until the rising edge t.sub.1 of the clock C sends out the input D to the output D.sub.1. As a result, input D is delayed by T'. D.sub.1 reaches DF.sub.2 slightly after the rising edge t.sub.1 of clock C reaches DF.sub.2. Therefore, D.sub.1 will be sent to the next flip flop DF.sub.3 on the rising edge t.sub.2 of the clock C. As a result, the delay created by DF.sub.2 is T which is equal to one cycle of clock C. In the same manner the delay created by DF.sub.3 and DF.sub.4 each is equal to one period T of the clock C.
The logic block diagram of FIG. 1 is a typical delay logic. Using this logic design requires a number of flip flops equal to the required number of delays. For example, if 32T delays are required, 32 flip flops will be needed. This design can become quite large if a delay of for example up to 64T is needed for 32 lines. This means that each line has to have 64 flip flops resulting in total 32.times.64=2068 flip flops.
It is an object of this invention to reduce the number of flip flops and the size and cost of a chip containing pulse width modulation circuit with plurality of delay requirements.